Silicon oxide films have process stability and excellent electrical insulation, and are being used for gate insulating materials of an MOSFET. With device miniaturization in recent years, thinning of a gate insulating film has been increasingly growing, and a device with a gate length of 100 nm or less requires a thickness of a silicon oxide film which is the gate insulating film, to be 1.5 nm or less from a requirement of the scaling law. However, if such an ultra-thin insulating film is used, upon applying gate bias voltage to a gate electrode, the magnitude of tunneling current sandwiched between a gate insulating layer and the gate electrode becomes an unignorable value against source/drain current, and exceeds a permissible range of device design. This would be a big barrier to promoting higher performance and lower power consumption of the MOSFET. Accordingly, research and development is proceeding with the aim to thin a film thickness of an effective gate insulating film and to control the tunneling current to within the permissible values.
One of them is a method of adding nitrogen into a silicon oxide film to thereby increase dielectric constant more than that of a pure silicon oxide film, and to reduce a film thickness of an effective, namely, electrical gate insulating layer without thinning a physical film thickness. Fabricating techniques of such a silicon oxynitride film include a method of making high-temperature heat treatment of the silicon oxide film in gas containing nitrogen such as ammonia (NH3) to thereby introduce the nitrogen into the silicon oxide film after forming the silicon oxide film on a surface of a silicon substrate. However, this method gives rise to a problem that the heat treatment in gas atmosphere causes segregation of the nitrogen into an interface between the silicon oxide film and the silicon substrate to produce deterioration of interface electrical characteristics. In the case of a silicon oxide film, it is generally possible to realize a good quality junction with less interface roughness and defect density. However, if a silicon oxynitride film is fabricated by the aforementioned technique, the interface roughness and the interface defect density will be increased by the segregated nitrogen in the interface.
Therefore, a technology (plasma nitriding technology) in which a silicon oxide film is exposed to nitrogen plasma to selectively nitride a surface side has been studied in recent years. In the technology applying this plasma, it is possible to control nitrogen concentration of an interface to a lower level and to minimize electrical characteristic deterioration caused by the aforementioned nitrogen. However, relative dielectric constant of a pure silicon oxynitride film is only twice as many as that of the silicon oxide film, and higher dielectric constant of an insulating film by nitrogen addition to the silicon oxide film has limitations. Thus increasing the relative dielectric constant to not less than 10 is impossible in principle.
Accordingly, as the next-generation technology in which the device miniaturization is moving ahead, an attempt is further being made to adopt thin film materials with relative dielectric constant of not less than 10, or a silicate thin film which is a composite material of these materials and silicon as the gate insulating film, in place of the silicon oxide film or an oxynitride film. As these high dielectric constant materials, Al2O3, ZrO2, or HfO2, and rare-earth element oxides such as Y2O3, and further lanthanoide rare earth element oxides such as La2O3 are being studied as candidate materials. This basis is that there exists a thickness that use of these high dielectric constant films would allow prevention of the tunneling current, while maintaining capacity of the gate insulating film in accordance with the scaling law, even if the gate length is miniaturized.
Note that assuming that the gate insulating materials are the silicon oxide films regardless of type of the gate insulating film, the film thickness obtained from back calculation of gate capacity is called Silicon Effective Oxide Thickness. More specifically, letting the relative dielectric constant of the insulating film and the relative dielectric constant of the silicon oxide film eh and eo, respectively, and the thickness of the insulating film dh, the Silicon Effective Oxide Thickness makes de=dh (eo/eh). This formula indicates that if a material having dielectric constant eh larger than eo is used, even an insulating film having a thick physical film thickness can be effectively and electrically equivalent to a thin silicon oxide film. The relative dielectric constant eo of the silicon oxide film is approximately 3.9, so that, for example, if a high dielectric film having relative dielectric constant eh=39 which is ten times as high as that is used, even the physical film thickness of the insulating film having a thickness of 15 nm will effectively and electrically make the Silicon Effective Oxide Thickness of 1.5 nm, enabling drastic reduction of the tunneling current.
In addition, each of a metal oxide and a silicate thin film features the following. If the metal oxides such as ZrO2 and HfO2 are used as a high dielectric constant gate insulating film, higher relative dielectric constant may be achieved. On the other hand, it is believed that although the relative dielectric constant decreases in a silicate material in which silicon is contained, thermal stability is enhanced, as well as the interface electrical characteristics may be improved as compared with the case where the metal oxides are directly joined onto the silicon substrate.
As described above, development of the next-generation MOSFET is considering to adopt the high dielectric constant thin film as the gate insulating film materials, and to adopt CVD (Chemical Vapor Deposition) using different kinds of source gas, or ALD (Atomic Layer Chemical Vapor Deposition) which controls CVD deposition on an atomic layer basis, as deposition techniques of the high dielectric constant thin film onto the surface of the silicon substrate.
In an initial stage of development of the high dielectric constant gate insulating film, a physical evaporation method such as sputtering, reactive sputtering, or Molecular Beam Deposition has been used with the aim of material search. In these deposition techniques, reported are examples in which a high dielectric constant film has been directly deposited on a surface of a silicon substrate, and in which an ultra-thin silicon oxide film, to be more precise, with a thickness of normally less than 1 nm, has been inserted into an interface between a high dielectric constant thin film and the silicon substrate for the purpose of controlling an early reaction of CVD or ALD deposition, and of improving thermal stability of the interface between the high dielectric constant thin film and the silicon substrate. In the latter case, the ultra-thin silicon oxide film is formed on the surface of the silicon substrate, and then the deposition of the high dielectric constant thin film is carried out by different kinds of deposition methods. Commonalties in these deposition techniques are that stoichiometric composition on the surface of the silicon substrate, or the deposition of the high dielectric constant film in agreement with silicate composition which is neither too much nor too little in oxygen concentration is necessary, and in particular, a structural defect such as an oxygen deficiency in a film causes deterioration of electrical characteristics and increase in leakage current.
With respect to various high dielectric constant materials fabricated by the aforementioned thin film deposition methods, the characteristics have been studied heretofore. Among these, the biggest technical problem toward the development of the next-generation MOSFET is improvement in the interface electrical characteristics between the high dielectric constant thin film and the silicon substrate. More specifically, the interface defect density between the high dielectric constant thin film interface and the silicon substrate is higher by one to two digits than the interface defect density between the silicon oxide film and the silicon substrate, deterioration of the mobility becomes significant due to charge captured by the interface defect, and current drive capability of the MOSFET declines. This cancels out the effect that the gate insulating film has been thinned.
As for means to improve the interface electrical characteristics, a structure in which the silicon oxide film is inserted into the interface between the high dielectric constant film and the silicon substrate as an interface oxide layer is being studied. An interface structure which determines the electrical characteristics is deeply related to a fabrication method of the high dielectric constant thin film. For example, even if the high dielectric constant thin film is directly deposited on the surface of the silicon substrate by means of the CVD or sputtering method, oxidation of the silicon substrate progresses concurrently with thin film deposition to form an interface layer mainly comprising the silicon oxide film when an oxidizing agent is introduced during the deposition, or when a large amount of residual oxygen are present within deposition apparatus. It is difficult to independently control the deposition of these interface layers, thus it being impossible to independently design the structure in which the interface electrical characteristics are optimized.
Meanwhile, techniques in which a silicon oxide film is intentionally inserted as an interface oxide layer include a method of forming an ultra-thin silicon oxide film on a surface of a silicon substrate in advance before depositing a high dielectric constant thin film, and a method of depositing a high dielectric constant thin film before giving heat treatment to allow growth of the silicon oxide film. The former method has an effect that insertion of the silicon oxide film enhances interface thermal stability. However, it is considered to be important that a film thickness of the ultra-thin silicon oxide film which is formed on the surface of the silicon substrate should be 0.6 nm or less due to low relative dielectric constant of the silicon oxide film. In addition, an ultra-thin base silicon oxide film is sometimes altered in a process of depositing the high dielectric constant thin film on the ultra-thin silicon oxide film, and hence interface characteristics between the ultra-thin silicon oxide film and the silicon substrate deteriorate. The latter method is a method utilizing phenomenon in which oxygen easily diffuses in the high dielectric constant thin film to form an interface layer. However, in the case where metal elements in the high dielectric constant film diffuse into the interface layer in a heat treatment process, it is impossible to form an ideal interface between the silicon oxide film and the silicon substrate excellent in the electrical characteristics.
In this way, the prior art had the problems that although in order to improve the interface electrical characteristics of the gate insulating film having high dielectric constant, formation of the high dielectric constant thin film excellent in film quality was necessary, while maintaining a good quality interface between the silicon oxide film and the silicon substrate, it was difficult to separate and control a forming process of the interface layer comprising the silicon oxide film, and a deposition process of the high dielectric constant film.